This invention relates to a delay test system of testing a normal circuit, such as an LSI.
Conventionally, a wide variety of tests have been performed to check whether or not each LSI is normally operated. In such tests, a delay test is included to test whether or not an undesirable delay takes place among logic circuits included in the LSI. To this end, a tester has been generally used to carry out the delay test of the LSI. In this event, the tester should generate a clock sequence of a high frequency and must have a very high performance. However, such a high performance tester is inevitably expensive.
On the other hand, it is a recent trend that an LSI is operated at a high speed and is therefore supplied with a very high frequency clock sequence. In order to test such an LSI operated at a high speed, a tester of the type described is also capable of supplying the LSI with a clock sequence of a high frequency. Otherwise, the delay test of such a high frequency LSI can not be preformed by the conventional tester of a low frequency. Under the circumstances, a delay test can not be practically performed by the use of the conventional tester.
Taking the above into consideration, some suggestions recently have been made about a method of performing the delay test with the tester having a low operation frequency. For instance, various methods have been disclosed in proceedings of International Test Conference 1995, page 302 to page 310, entitled "High-Performance Circuit Testing with Slow-Spend Testers".
However, each of the testers should have a large amount of overhead with respect to the LSI structure. To avoid this, it is necessary to broadly change a conventional method of designing the LSI.
From this fact, it is readily understood that a conventional delay test method requires the high-speed tester. Further, when the high-speed tester is not required, a large amount of overhead is inescapably required to perform the delay test. Moreover, the method of designing the normal circuit must be also changed to effectively perform the conventional delay test in connection with a high speed LSI.